1. Field of the Invention
The present invention relates to semiconductor device structures and, in particular, to electrostatic discharge protection structures for use with integrated circuits.
2. Description of the Related Art
Electrostatic discharge (ESD) protection devices are commonly employed in an integrated circuit (IC) to protect electronic devices in the IC from spurious pulses of excessive voltage (e.g., an ESD event, Human Body Model [HBM] event, or Electrical Overstress [EOS] event). See, for example, S. M. Sze, Electrostatic Discharge Damage, in VLSI Technology, Second Edition, 648–650 (McGraw Hill, 1988). A variety of conventional ESD protection devices that make extensive use of diodes, metal-oxide-semiconductor field effect transistors (MOSFETs), and bipolar transistors are known in the field. For example, conventional ESD protection devices for use with CMOS integrated circuits include Grounded Gate MOS (GGMOS) ESD protection structures and Low Voltage Silicon Controlled Rectifier (LVSCR) ESD protection structures. Descriptions of these and other conventional ESD protection structures are available in Haigang, et al., A Comparison Study of ESD Protection for RFICs: Performance vs. Parasitics, 2000 IEEE Radio Frequency Integrated Circuits Symposium, 235–237 (2000); U.S. patent application for “MOSFET Structure For Use in ESD Protection Devices” (filed Jul. 17, 2000; application number not yet assigned) and U.S. patent application Ser. No. 09/205,110 (filed Dec. 3, 1998), each of which is hereby fully incorporated by reference.
Conventional MOSFET structures are designed to exhibit breakdown characteristics only at voltages well above their standard operating supply voltage. However, during an ESD event, GGMOS ESD structures exhibit current conduction via a parasitic lateral bipolar mechanism. For a further description of current conduction in GGMOS ESD structures via a parasitic lateral bipolar mechanism, see E. A. Amerasekera et al., ESD in Silicon Integrated Circuits, sections 3.5.2 and 3.6 (John Wiley & Sons, 1995), which are hereby fully incorporated by reference.
ESD events can be of either a negative polarity or a positive polarity. Conventional GGMOS or LVSCR ESD protection structures can only protect electronic devices in an IC from a single polarity ESD event. Thus, two such structures are required to protect electronic devices in an IC from ESD events of both polarities.
The ESD protection capability of ESD protection devices is characterized by their snapback holding voltage and their maximum snapback current. ESD protection capability is improved at lower snapback holding voltages and higher maximum snapback current. Conventional GGMOS and LVSCR ESD protection structures operate via an avalanche-injection conductivity modulation mechanism. This mechanism, however, provides a relatively high snapback holding voltage and a relatively low snapback current.
Still needed in the field, therefore, is an ESD protection structure that can protect electronic devices in an IC from ESD events of both positive and negative polarities, has a low snapback holding voltage and a high maximum snapback current.